[PATCH] D103787: [RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.

[Craig Topper via Phabricator via llvm-commits]

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This can cause the vectorizer to generate interleaved scalar
code which might be ok for some CPUs, but definitely not all.
Disable it to restore the previous scalar behavior.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103787

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.h


Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -135,7 +135,9 @@
     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
     return UserReservedRegister[i];
   }
-  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
+  unsigned getMaxInterleaveFactor() const {
+    return hasStdExtV() ? MaxInterleaveFactor : 1;
+  }
 
 protected:
   // GlobalISel related APIs.


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