[PATCH] D103299: [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 349591.
craig.topper added a comment.

Rename variable and clean up comments to hopefully make things more clear.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103299/new/

https://reviews.llvm.org/D103299

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
  llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

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