[PATCH] D103299: [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.

Fraser Cormack via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 3 02:18:07 PDT 2021


frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:183
 
-    // VTypes must match.
-    if (!hasSameVTYPE(Other))
+    // VTypes must match unless this is a mask reg operation, then we only care
+    // about VLMAX.
----------------
I'm finding this comment a little confusing in that it says "unless this is a mask reg operation" but only (explicitly) checks `Other.MaskRegOp`. Is "this" implied, or should the comment be updated?


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  https://reviews.llvm.org/D103299/new/

https://reviews.llvm.org/D103299



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