[PATCH] D103299: [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.
Hsiangkai Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 1 22:08:06 PDT 2021
HsiangKai added a comment.
LGTM.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D103299/new/
https://reviews.llvm.org/D103299
More information about the llvm-commits
mailing list