[PATCH] D103174: RISCV: honour `.option relax` in assembly

[Saleem Abdulrasool via Phabricator via llvm-commits]

compnerd updated this revision to Diff 349309.
compnerd marked an inline comment as done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103174/new/

https://reviews.llvm.org/D103174

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
  llvm/test/MC/RISCV/scoped-relaxation.s


Index: llvm/test/MC/RISCV/scoped-relaxation.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/scoped-relaxation.s
@@ -0,0 +1,30 @@
+# RUN: llvm-mc -mattr -relax -triple riscv64-unknown-none-elf -filetype obj %s -o - | llvm-readobj -d -r - | FileCheck %s
+
+.global function
+
+# Unrelaxed reference, this would normally fail, but the subsequent scoped
+# relaxation forces relaxation on the file.
+.dword function - .
+
+# CHECK: 0x0 R_RISCV_ADD64 function 0x0
+# CHECK: 0x0 R_RISCV_SUB64 - 0x0
+
+# Relaxed reference, this will resolve to a pair of `RISCV_ADD64` and
+# `RISCV_SUB64` relocation.
+.option push
+.option relax
+.dword function - .
+.option pop
+
+# CHECK: 0x8 R_RISCV_ADD64 function 0x0
+# CHECK: 0x8 R_RISCV_SUB64 - 0x0
+
+# Unrelaxed reference, this will resolve to a pair of `RISCV_ADD64` and
+# `RISCV_SUB64` relocation due to relaxation being sticky to the file.
+.option push
+.option norelax
+.dword function - .
+.option pop
+
+# CHECK: 0x10 R_RISCV_ADD64 function 0x0
+# CHECK: 0x10 R_RISCV_SUB64 - 0x0
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -70,29 +70,33 @@
 void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {
+  MCAssembler &MCA = getStreamer().getAssembler();
+  auto &MAB = static_cast<RISCVAsmBackend &>(MCA.getBackend());
+  MAB.setForceRelocs();
+}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}

 void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
   setAttributeItem(Attribute, Value, /*OverwriteExisting=*/true);
 }

 void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute,
                                                StringRef String) {
   setAttributeItem(Attribute, String, /*OverwriteExisting=*/true);
 }

 void RISCVTargetELFStreamer::emitIntTextAttribute(unsigned Attribute,
                                                   unsigned IntValue,
                                                   StringRef StringValue) {
   setAttributeItems(Attribute, IntValue, StringValue,
                     /*OverwriteExisting=*/true);
 }

 void RISCVTargetELFStreamer::finishAttributeSection() {
   if (Contents.empty())
     return;

   if (AttributeSection) {
     Streamer.SwitchSection(AttributeSection);
   } else {


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