[PATCH] D102521: [RISCV] Optimize SEW=64 shifts by splat on RV32.

Wed May 26 09:30:14 PDT 2021

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

In D102521#2777568 <https://reviews.llvm.org/D102521#2777568>, @craig.topper wrote:

> In D102521#2777262 <https://reviews.llvm.org/D102521#2777262>, @frasercrmck wrote:
>
>> I probably don't have the full picture here, but I was wondering if there was a generic "simplify demanded bits" we could hook this node into, since presumably LLVM already knows that only those bits of the shift are used. Does `SimplifyDemandedBitsForTargetNode` not apply here?
>
> I think for generic shift, nodes llvm considers all bits of the shift amount to be demanded. It's not generally safe because not all targets have shift instructions that modulo the shift amount.

Interesting, that makes sense. Thanks.

Then this is probably the best way of doing it. LGTM.

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https://reviews.llvm.org/D102521