[PATCH] D102737: [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

This is looking great.

I was wondering if we can delay all the insertions to phase 3. I understand this would require keep tracking the insertion points. I mention that because it could help if we want to be able to simplify further the insertion points after phase1 or phase2. In that setting, phase 1 could be named something like `computeDemandedVSETVL`, phase 2 could be `computeIncomingVLVTYPE` and then phase 3 `emitVSETVL`

An example of possible optimization, could be a loop that loads SEW=32 vectors and does a widening operation (say `vfwmac`) and stores the resulting SEW=64 (without further processing that vector) using `vse64`. Looks to me we could just go with a single `vsetvl` here with SEW=32.

What do you think?



================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:317
+  BlockData &BBInfo = BlockInfo[MBB.getNumber()];
+  // RequirePending is used to indicate whether we are collecting the initial
+  // requirements for the block.
----------------
Not sure what this `RequirePending` refers to?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102737/new/

https://reviews.llvm.org/D102737