[PATCH] D102737: [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:301
+    Register AVLReg = MI.getOperand(1).getReg();
+    assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
+           "Can't handle X0, X0 vsetvli yet");
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is the assertion avoidable by doing `setAVLReg(RISCV::NoRegister)` for vtype-only change,  and something like
`BBInfo.change = Merge(BBInfo.change, getInfoForVSETVLI)` to keep the latest VL & vtype change ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102737/new/

https://reviews.llvm.org/D102737