[PATCH] D102737: [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: frasercrmck, evandro, HsiangKai, rogfer01, arcbbb, khchen.
Herald added subscribers: StephenFan, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, mgorny, qcolombet.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.
Herald added a project: LLVM.

This is a replacement for D101938 <https://reviews.llvm.org/D101938> for inserting vsetvli
instructions where needed. This new version changes how
we track the information in such a way that we can extend
it to be aware of VL/VTYPE changes in other blocks. Given
how much it changes the previous patch, I've decided to
abandon the previous patch and post this from scratch.

The pass now consists of 3 phases. The first phase inserts
intra block vsetvlis and collects the requirements for the
first instruction in the block. The second phase calculates
the incoming value for each block. The third phase checks
the requirements against the incoming value and inserts a
vsetvli if needed.

For now I've stubbed out phase 2 to make it equivalent to
D101938 <https://reviews.llvm.org/D101938>. The only change from the tests in D101938 <https://reviews.llvm.org/D101938> is the
numbering of virtual registers in one test in vsetvli-insert.mir.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102737

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
  llvm/test/CodeGen/RISCV/rvv/cleanup-vsetivli.mir
  llvm/test/CodeGen/RISCV/rvv/cleanup-vsetvli.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
  llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
  llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
  llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

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