[PATCH] D102606: [RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns

[Fraser Cormack via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG175bdf127d5b: [RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns (authored by frasercrmck).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102606/new/

https://reviews.llvm.org/D102606

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll

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