[PATCH] D102606: [RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns

Tue May 18 01:53:34 PDT 2021

frasercrmck added a comment.

In D102606#2764127 <https://reviews.llvm.org/D102606#2764127>, @craig.topper wrote:

> LGTM.  Let's try to get it into the 12.0.1 release.

My bad, it seems that the 12 release doesn't have the fixed-length RVV support. Time flies.

In D102606#2764964 <https://reviews.llvm.org/D102606#2764964>, @jrtc27 wrote:

> Does the `vs2, vs1` operand order in the spec make sense? Would `vs1, vs2` not be more natural?

To me, `vs1,vs2` would certainly be more natural and it is indeed `vs1,vs2` in a select few operations. To be honest, I can't think of a way that it //has// to be the way it is. Perhaps it's more consistent and requires fewer unique operand names across the full instruction set.

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https://reviews.llvm.org/D102606