[PATCH] D102606: [RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Does the `vs2, vs1` operand order in the spec make sense? Would `vs1, vs2` not be more natural?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102606/new/

https://reviews.llvm.org/D102606