[PATCH] D102333: [AArch64] Combine shift instructions in SelectionDAG

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

This sound interesting, but there might be a more general way to handle it. From what I can tell the base sshr demands a certain number of top bits. That is usually communicated through TLI.SimplifyDemandedBits with an appropriate DemandedMask.

Then I think it could specify the simplification that happens to target nodes based on demanded bits with an overridden SimplifyDemandedBitsForTargetNode. It would need code similar to https://github.com/llvm/llvm-project/blob/4f05f4c8e66bc76b1d94f5283494404382e3bacd/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L1455, but using AArch64ISD::VSHL/AArch64ISD::VLSHR.

That might be more general, handling any cases where the demanded bits come from anywhere. And SimplifyDemandedBitsForTargetNode can be expanded with more cases if we find them.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14562
+static int64_t getShiftImm(SDNode *Shift) {
+  if (auto *Imm = dyn_cast<ConstantSDNode>(Shift->getOperand(1)))
+    return Imm->getSExtValue();
----------------
I think that the shift amount of VASHR/VLSHR/VSHL are always constants, so Op0.getConstantOperandVal(1) can be used directly.


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https://reviews.llvm.org/D102333