[PATCH] D102333: [AArch64] Combine shift instructions in SelectionDAG
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 13 23:00:12 PDT 2021
dmgreen added a comment.
If you want to do it this way instead though, that sounds fine too. There will only be a limited number of cases where the AArch64ISD::VSHL etc haven't already been simplified.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14575
+
+ SDNode *Shift2 = Shift1->getOperand(0).getNode();
+ unsigned Shift2Opc = Shift2->getOpcode();
----------------
SDValue Shift2 = Shift1->getOperand(0);
Same for Shift3 below.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14581
+ SDNode *Shift3 = Shift2->getOperand(0).getNode();
+ unsigned Shift3Opc = Shift3->getOpcode();
+ if (Shift3Opc != AArch64ISD::VLSHR)
----------------
This is only used in one place. Same for Shift2Opc above.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14602
+ }
+ for (SDNode *User : Shift3->uses()) {
+ if (User != Shift2)
----------------
I believe these could both just be hasOneUse()
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14608
+ SDValue Ops[] = {Shift3->getOperand(0), Shift1->getOperand(1)};
+ return DAG.getNode(Shift1->getOpcode(), SDLoc(Shift1),
+ Shift1->getValueType(0), Ops);
----------------
Shift1Opc
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https://reviews.llvm.org/D102333/new/
https://reviews.llvm.org/D102333
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