[PATCH] D101992: AMDGPU/GlobalISel: Use destination register bank in applyMappingLoad

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Can you also add an end to end IR test for this case



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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll:449-452
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 s2, -1
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 s3, 0xf000
+; GFX7-UNALIGNED-NEXT:    buffer_load_dwordx3 v[0:2], off, s[0:3], 0
+; GFX7-UNALIGNED-NEXT:    s_waitcnt vmcnt(0)
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This looks like an accidental bug fix


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir:4-14
+
+--- |
+  define amdgpu_ps void @test_uniform_load_without_noclobber(<16 x float> addrspace(1)* inreg %inaddr, <16 x float> addrspace(1)* inreg %outaddr) #0 {
+  entry:
+    %load = getelementptr <16 x float>, <16 x float> addrspace(1)* %inaddr, i64 0, !amdgpu.uniform !0
+    %in = load <16 x float>, <16 x float> addrspace(1)* %load, align 4
+    store <16 x float> %in, <16 x float> addrspace(1)* %outaddr, align 4
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Don't need the IR section, just mark the MMOs as invariant


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  https://reviews.llvm.org/D101992/new/

https://reviews.llvm.org/D101992