[PATCH] D101164: [CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:19060
 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
+  // At -O0 expand pseudo-instructions after register allocation to avoid
+  // inserting spills between ldrex/strex.
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chill wrote:
> Why are we doing this only at `-O0` ?
As far as we know, the problem with spills only shows up with fast regalloc (i.e. at -O0).  Using the pesudo-instruction at other optimization levels is possible, but I'm not sure what the performance implications would be.


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  https://reviews.llvm.org/D101164/new/

https://reviews.llvm.org/D101164