[PATCH] D101164: [CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0

[Momchil Velikov via Phabricator via llvm-commits]

chill added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:19060
 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
+  // At -O0 expand pseudo-instructions after register allocation to avoid
+  // inserting spills between ldrex/strex.
----------------
Why are we doing this only at `-O0` ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101164/new/

https://reviews.llvm.org/D101164