[PATCH] D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

The splice tests show two issues:

1. We don't care about the number of uses of the address; this can lead to an extra loop-invariant instruction if one of the operands of the add is a small constant.  This is a issue with all patterns using the am_sve_regreg_lsl0 matcher; see the generated code for splice_nxv16i1. This seems like an edge case... you specifically need a small constant offset, and the current formulation probably has lower latency.  If you think it's worth addressing, I can try messing with the matcher.
2. We generate an extra ptrue because of the element width.  The ptrue thing seems like a general issue we'd want to address elsewhere; not sure it should block this.

> Is there a way to know if the basic block is, or within, a loop body?

SelectionDAGISel has LoopInfo, so in theory, we could compute it?  But I don't think we pass through the information at the moment.


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https://reviews.llvm.org/D100527