[PATCH] D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Are we concerned about the reduced code quality shown by the splice tests? Is there a way to know if the basic block is, or within, a loop body? so that we can restrict the patterns to instances where we're confident the extra instructions are likely to be hoisted.  I guess for the `PTRUE` case we already know there is a need for some kind of machine pass to remove larger element `PTRUE`s when a smaller element one is safe to use.



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Comment at: llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll:1166-1168
 ; CHECK-NEXT:    addvl x8, x8, #2
+; CHECK-NEXT:    ld1b { z0.b }, p1/z, [x8, x9]
 ; CHECK-NEXT:    sub x8, x8, #32 // =32
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This suggest we should limit the usage to only when there's a single use of the address? or more precisely not kick in unless we can guarantee the add/sub will be omitted.


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  https://reviews.llvm.org/D100527/new/

https://reviews.llvm.org/D100527