[PATCH] D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes

[Eli Friedman via Phabricator via llvm-commits]

efriedma updated this revision to Diff 341620.
efriedma edited the summary of this revision.
efriedma added a comment.

Updated to handle other relevant types.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100527/new/

https://reviews.llvm.org/D100527

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
  llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D100527.341620.patch
Type: text/x-patch
Size: 15141 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210429/f5d5f831/attachment.bin>