[PATCH] D101465: [RISCV] Lower splats of non-constant i1s as SETCCs
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 29 01:38:48 PDT 2021
frasercrmck added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1365
+ MVT InterVT = VT.changeVectorElementType(MVT::i8);
+ Splat = DAG.getSplatBuildVector(InterVT, DL, Splat);
+ SDValue Zero = DAG.getConstant(0, DL, InterVT);
----------------
craig.topper wrote:
> Don't we need to mask out all but bit 0 of Splat? I don't think those bits are defined.
Yeah I think you're right. I was going by the "zero or one" boolean contents contract which I thought covered us when the i1s were widened to XLEN but, thinking about it, that probably doesn't cover the operands of `BUILD_VECTOR` or `SPLAT_VECTOR`. Right?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D101465/new/
https://reviews.llvm.org/D101465
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