[PATCH] D101465: [RISCV] Lower splats of non-constant i1s as SETCCs

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1365
+      MVT InterVT = VT.changeVectorElementType(MVT::i8);
+      Splat = DAG.getSplatBuildVector(InterVT, DL, Splat);
+      SDValue Zero = DAG.getConstant(0, DL, InterVT);
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Don't we need to mask out all but bit 0 of Splat? I don't think those bits are defined.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101465/new/

https://reviews.llvm.org/D101465