[PATCH] D101465: [RISCV] Lower splats of non-constant i1s as SETCCs

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1365
+      MVT InterVT = VT.changeVectorElementType(MVT::i8);
+      Splat = DAG.getSplatBuildVector(InterVT, DL, Splat);
+      SDValue Zero = DAG.getConstant(0, DL, InterVT);
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frasercrmck wrote:
> craig.topper wrote:
> > Don't we need to mask out all but bit 0 of Splat? I don't think those bits are defined.
> Yeah I think you're right. I was going by the "zero or one" boolean contents contract which I thought covered us when the i1s were widened to XLEN but, thinking about it, that probably doesn't cover the operands of `BUILD_VECTOR` or `SPLAT_VECTOR`. Right?
It applies to the output of SETCC or the expectations of SELECT. But the i1 could have been produced by a TRUNCATE for example in which case it wouldn't have to respect boolean contents. 

DAG combine should be able to delete the AND if the input came from SETCC, though X86 detects that case directly in lowering. See LowerBUILD_VECTORvXi1 right around the FIXME comment in that function.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101465/new/

https://reviews.llvm.org/D101465