[PATCH] D101215: [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1170
     // the most elements.
+    // FIXME: We're limiting to LMUL 1,2,4,8. Should we support fractional?
     MinVLen /= 8;
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I do wonder about this. So with min=128, a `v2i1` would use a `nxv8i1` container type, but `v2i8 => nxv1i8`? Might that make certain operations more difficult if we don't have legal `nxv1i1`, `nxv2i1`, `nxv4i1`?


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  https://reviews.llvm.org/D101215/new/

https://reviews.llvm.org/D101215