[PATCH] D101215: [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1170
     // the most elements.
+    // FIXME: We're limiting to LMUL 1,2,4,8. Should we support fractional?
     MinVLen /= 8;
----------------
frasercrmck wrote:
> I do wonder about this. So with min=128, a `v2i1` would use a `nxv8i1` container type, but `v2i8 => nxv1i8`? Might that make certain operations more difficult if we don't have legal `nxv1i1`, `nxv2i1`, `nxv4i1`?
`nxv1i1`, `nxv2i1`, `nxv4i1` are legal types they just won't be selected for mask only operations like vmand, vmor, vmxor, etc. They will be used for setcc results.   Masks are messed up because a v2i16 setcc would use nxv1i16(lmul 1/4) and v2i8 setcc would use nxv1i8(lmul 1/8). We use nxv1i1 for the mask type for both. To minimize vsetvli changes vmand/vmor/vmxor/etc operations on the mask should use nxv2i1 if the producer was v2i16 or nxv1i1 if the producer was v2i8.

I think enabling fractional lmul here would make the i8 case correct but everything else would still be wrong. I guess I don't have a good reason not to do it. I'll try it and see what happens.


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  https://reviews.llvm.org/D101215/new/

https://reviews.llvm.org/D101215