[PATCH] D101215: [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1184
+    // We prefer to use LMUL=1 for VLEN sized types. Use fractional lmuls for
+    // narrower types, but we can't go below LMUL=64/SEW.
     unsigned EltsPerBlock = RISCV::RVVBitsPerBlock / EltVT.getSizeInBits();
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frasercrmck wrote:
> Maybe this comment could be corrected/clarified. I see what it's trying to convey but saying we can't go below `LMUL=64/SEW` makes it sound like we can't have fractional types at all since they'd always be at least 1.
Oops I think I was thinking in terms of the denominator when I wrote that. So it's really SEW/64.


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  https://reviews.llvm.org/D101215/new/

https://reviews.llvm.org/D101215