[PATCH] D101465: [RISCV] Lower splats of non-constant i1s as SETCCs
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 28 08:26:42 PDT 2021
frasercrmck added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll:167
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmsne.vi v0, v26, 0
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I was wondering if `vmv.v.i v26, 0 ; vmsne.vx v0, v26, a0` would be faster. Any insights there?
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D101465/new/
https://reviews.llvm.org/D101465
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