[PATCH] D101455: [ELF] Implement RISCV::getImplicitAddend()
Jessica Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 28 07:17:43 PDT 2021
jrtc27 added a comment.
In D101455#2722743 <https://reviews.llvm.org/D101455#2722743>, @arichardson wrote:
> In D101455#2722721 <https://reviews.llvm.org/D101455#2722721>, @jrtc27 wrote:
>
>> Honestly this seems rather academic, surely we should just mandate Elf_Rela for RISC-V? I've filed https://github.com/riscv/riscv-elf-psabi-doc/issues/186.
>
> I don't think this should be a supported configuration, but it appears that `-z rel` is being used with AArch64, so it might make sense to allow it for RISC-V too.
AAELF64 explicitly permits both, whereas RISC-V is silent on the matter and AFAIK nobody is using Elf_Rel because why would you inflict that pain upon yourself.
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https://reviews.llvm.org/D101455/new/
https://reviews.llvm.org/D101455
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