[PATCH] D101383: Disable vinsw, vinsd, and vins[wd][lr]x P10 instructions in P10

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10344
     // integer vectors.
     if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
         VT == MVT::v2i64)
----------------
It would seem that all we need to change this condition and the one below to not emit `PPCISD::VECINSERT` for 64-bit element widths (`v2i64, v2f64`). Why do we need to disable this lowering on 32-bit targets altogether?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101383/new/

https://reviews.llvm.org/D101383