[PATCH] D101383: Disable vinsw, vinsd, and vins[wd][lr]x P10 instructions in P10

[Zarko Todorovski via Phabricator via llvm-commits]

ZarkoCA added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10344
     // integer vectors.
     if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
         VT == MVT::v2i64)
----------------
nemanjai wrote:
> It would seem that all we need to change this condition and the one below to not emit `PPCISD::VECINSERT` for 64-bit element widths (`v2i64, v2f64`). Why do we need to disable this lowering on 32-bit targets altogether?
It looks like all of the pattern matches for VINS* in `PPCInstrPrefix.td` hardcode `i64`:
eg:
```
  def : Pat<(v16i8 (PPCvecinsertelt v16i8:$vDi, i32:$rA, i64:$rB)),
            (VINSBLX $vDi, InsertEltShift.Sub32Left0, $rA)>;
...
 foreach i = [0, 1] in
    def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, (i64 i))),
              (VINSD $vDi, !mul(i, 8), $rA)>;
}
```
So we can't emit the VECINSERT safely in 32bit mode due to this. 


Repository:
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  https://reviews.llvm.org/D101383/new/

https://reviews.llvm.org/D101383