[PATCH] D100430: [AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:446
                        AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT;
-
-  // There are no extending SMRD/SMEM loads, and they require 4-byte alignment.
-  return MMO->getSize() >= 4 && MMO->getAlign() >= Align(4) &&
+  // Require 4-byte alignment.
+  return MMO->getAlign() >= Align(4) &&
----------------
The old comment was more informative


================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir:245
+    %1:_(s32) = G_SEXTLOAD %0 :: (invariant load 2, align 2, addrspace 4 )
+...
+---
----------------
Should add some dummy uses, e.g. S_ENDPGM 0, implicit %1

Just in case regbankselect decides to start dropping dead uses someday


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100430/new/

https://reviews.llvm.org/D100430