[PATCH] D100566: [SCEV] Add a ah-hoc pattern on isImpliedCondBalancedTypes

JinGu Kang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 15 08:08:53 PDT 2021

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jaykang10 added a comment.

@reames I am aiming to handle more cases on IRCE pass. If you think SCEV is not good place for this change, please let me know. I could move this change to IRCE pass.


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  https://reviews.llvm.org/D100566/new/

https://reviews.llvm.org/D100566

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