[PATCH] D100566: [SCEV] Add a ah-hoc pattern on isImpliedCondBalancedTypes

[JinGu Kang via Phabricator via llvm-commits]

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I have seen some cases which SCEV's `isImpliedCond` returns false.

It looks `isImpliedCond' has no patterns for case which the FoundLHS or FoundRHS is AddRec and the LHS and RHS are not AddRec.

In order to handle this case, we can use below one.

If FoundRHS is AddRec and FoundPred is EQ, we can say

      

The min value of FoundRHS is AddRec's start value if and only if "AddRec == FoundRHS" is true.

      

It means we can use "FoundRHS >= AddRec's start value" for "AddRec == FoundRHS".

This changes helps IRCE pass handles cascaded sibling loops.


https://reviews.llvm.org/D100566

Files:
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/test/Transforms/IRCE/sibling_loops.ll
  llvm/test/Transforms/IndVarSimplify/ARM/indvar-cost.ll
  llvm/test/Transforms/IndVarSimplify/lftr-pr20680.ll

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