[PATCH] D98101: [RISCV] Enable the LocalStackSlotAllocation pass support

[luxufan via Phabricator via llvm-commits]

StephenFan marked 9 inline comments as done.
StephenFan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:300
+// served by a base register other than FP or SP.
+// Used by LocalStackSlotAllocation to determine which frame index references it
+// should create new base registers for.
----------------
asb wrote:
> I think this sentence needs rewriting - I can't quite follow it.
emm, This sentence is copied from TargetRegisterInfo.h. It means that, For RISCV, if a frame index operand has a Offset that out-of-range 12 bits, this function will return true to indicate this frame index operand needs a frame base register.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98101/new/

https://reviews.llvm.org/D98101