[PATCH] D100424: [RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

Seems like a decent cleanup to me.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:130
-              opcodestr, "$rd, $rs1, $shamt"> {
-  bits<6> shamt;
-
----------------
So this was a 6-bit field even though the instruction only takes 4/5 bits through `shfl_uimm`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100424/new/

https://reviews.llvm.org/D100424