[PATCH] D100424: [RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:130
-              opcodestr, "$rd, $rs1, $shamt"> {
-  bits<6> shamt;
-
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frasercrmck wrote:
> So this was a 6-bit field even though the instruction only takes 4/5 bits through `shfl_uimm`?
Yeah. Maybe it was trying to cover for RV128 because that's how the spec is written. But the other shifts just put a 0 where the extra bit of shift amount goes so if it was it wasn't consistent.


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  https://reviews.llvm.org/D100424/new/

https://reviews.llvm.org/D100424