[PATCH] D100424: [RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.

[Craig Topper via Phabricator via llvm-commits]

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This generalizes RVInstIShift/RVInstIShiftW to take the upper
5 or 7 bits of the immediate as an input instead of only bit 30. Then
we can share them.

For RVInstIShift I left a hardcoded 0 at bit 26 where RV128 gets
a 7th bit for the shift amount.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100424

Files:
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td

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