[PATCH] D99966: [X86][AMX] Refactor for PostRA ldtilecfg pass.

[Xiang Zhang via Phabricator via llvm-commits]

xiangzhangllvm added inline comments.


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Comment at: llvm/lib/Target/X86/X86TileConfig.cpp:123
+    unsigned Index = VRM.getPhys(VirtReg) - X86::TMM0;
+    if (!Phys2Virt[Index])
+      Phys2Virt[Index] = VirtReg;
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I see here suppose all virtual tile regs are same shape, how we handle the cfg for tileload/store at spill ?


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  https://reviews.llvm.org/D99966/new/

https://reviews.llvm.org/D99966