[llvm] cb4c793 - [RISCV] Update computeKnownBitsForTargetNode to treat READ_VLENB as being 16 byte aligned.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-04-11T17:54:23-07:00
New Revision: cb4c793e46bb01914e07d1c66238133e6d672321

URL: https://github.com/llvm/llvm-project/commit/cb4c793e46bb01914e07d1c66238133e6d672321
DIFF: https://github.com/llvm/llvm-project/commit/cb4c793e46bb01914e07d1c66238133e6d672321.diff

LOG: [RISCV] Update computeKnownBitsForTargetNode to treat READ_VLENB as being 16 byte aligned.

According to the 0.10 spec, VLEN is at least 128 bits and is a
power of 2.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b02140a7ada9..6df181ee0645 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1704,6 +1704,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     // We define our scalable vector types for lmul=1 to use a 64 bit known
     // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
     // vscale as VLENB / 8.
+    assert(RISCV::RVVBitsPerBlock == 64 && "Unexpected bits per block!");
     SDValue VScale = DAG.getNode(ISD::SRL, DL, VT, VLENB,
                                  DAG.getConstant(3, DL, VT));
     return DAG.getNode(ISD::MUL, DL, VT, VScale, Op.getOperand(0));
@@ -5338,9 +5339,8 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     break;
   }
   case RISCVISD::READ_VLENB:
-    // We assume VLENB is at least 8 bytes.
-    // FIXME: The 1.0 draft spec defines minimum VLEN as 128 bits.
-    Known.Zero.setLowBits(3);
+    // We assume VLENB is at least 16 bytes.
+    Known.Zero.setLowBits(4);
     break;
   }
 }