[PATCH] D100135: [AMDGPU] Check for all meta instrs in GCNRegBankReassign
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 8 13:41:23 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG627dab3dbfc9: [AMDGPU] Check for all meta instrs in GCNRegBankReassign (authored by rampitec).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D100135/new/
https://reviews.llvm.org/D100135
Files:
llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
Index: llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
+++ llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
@@ -572,3 +572,40 @@
%4 = V_ADD_F64_e64 0, %0.sub0_sub1:vreg_128, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec
S_ENDPGM 0
...
+
+# GCN-LABEL: dbg_value_v1_v5{{$}}
+# GCN: renamable $vgpr1 = IMPLICIT_DEF
+# GCN: renamable $vgpr5 = IMPLICIT_DEF
+---
+name: dbg_value_v1_v5
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: '$vgpr1' }
+ - { id: 1, class: vgpr_32, preferred-register: '$vgpr5' }
+ - { id: 2, class: vgpr_32 }
+body: |
+ bb.0:
+ %0 = IMPLICIT_DEF
+ %1 = IMPLICIT_DEF
+ DBG_VALUE debug-use %1, debug-use %0
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+
+# GCN-LABEL: kill_v1_v5{{$}}
+# GCN: renamable $vgpr1 = IMPLICIT_DEF
+# GCN: renamable $vgpr5 = IMPLICIT_DEF
+# GCN: KILL killed renamable $vgpr5, killed renamable $vgpr1
+---
+name: kill_v1_v5
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: '$vgpr1' }
+ - { id: 1, class: vgpr_32, preferred-register: '$vgpr5' }
+ - { id: 2, class: vgpr_32 }
+body: |
+ bb.0:
+ %0 = IMPLICIT_DEF
+ %1 = IMPLICIT_DEF
+ KILL %1, %0
+ S_ENDPGM 0
+...
Index: llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
+++ llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
@@ -397,7 +397,7 @@
unsigned StallCycles = 0;
unsigned UsedBanks = 0;
- if (MI.isDebugValue())
+ if (MI.isMetaInstruction())
return std::make_pair(StallCycles, UsedBanks);
if (!(Mode & RM_SGPR) &&
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