[llvm] 627dab3 - [AMDGPU] Check for all meta instrs in GCNRegBankReassign

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2021-04-08T13:41:10-07:00
New Revision: 627dab3dbfc9f0c38363c5c2b6d8ce1b22395ae5

URL: https://github.com/llvm/llvm-project/commit/627dab3dbfc9f0c38363c5c2b6d8ce1b22395ae5
DIFF: https://github.com/llvm/llvm-project/commit/627dab3dbfc9f0c38363c5c2b6d8ce1b22395ae5.diff

LOG: [AMDGPU] Check for all meta instrs in GCNRegBankReassign

It used to work correctly even with a KILL, but there is
no reason to consider meta instructions since they do not
create real HW uses.

Differential Revision: https://reviews.llvm.org/D100135

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
    llvm/test/CodeGen/AMDGPU/regbank-reassign.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
index 0e7041c89864a..085796dee08b8 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
@@ -397,7 +397,7 @@ GCNRegBankReassign::analyzeInst(const MachineInstr &MI, Register Reg,
   unsigned StallCycles = 0;
   unsigned UsedBanks = 0;
 
-  if (MI.isDebugValue())
+  if (MI.isMetaInstruction())
     return std::make_pair(StallCycles, UsedBanks);
 
   if (!(Mode & RM_SGPR) &&

diff  --git a/llvm/test/CodeGen/AMDGPU/regbank-reassign.mir b/llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
index f904763e0a2f4..df057da98c2bf 100644
--- a/llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
+++ b/llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
@@ -572,3 +572,40 @@ body: |
     %4 = V_ADD_F64_e64 0, %0.sub0_sub1:vreg_128, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec
     S_ENDPGM 0
 ...
+
+# GCN-LABEL: dbg_value_v1_v5{{$}}
+# GCN: renamable $vgpr1 = IMPLICIT_DEF
+# GCN: renamable $vgpr5 = IMPLICIT_DEF
+---
+name:            dbg_value_v1_v5
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '$vgpr1' }
+  - { id: 1, class: vgpr_32, preferred-register: '$vgpr5' }
+  - { id: 2, class: vgpr_32 }
+body: |
+  bb.0:
+    %0 = IMPLICIT_DEF
+    %1 = IMPLICIT_DEF
+    DBG_VALUE debug-use %1, debug-use %0
+    S_ENDPGM 0, implicit %0, implicit %1
+...
+
+# GCN-LABEL: kill_v1_v5{{$}}
+# GCN: renamable $vgpr1 = IMPLICIT_DEF
+# GCN: renamable $vgpr5 = IMPLICIT_DEF
+# GCN: KILL killed renamable $vgpr5, killed renamable $vgpr1
+---
+name:            kill_v1_v5
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '$vgpr1' }
+  - { id: 1, class: vgpr_32, preferred-register: '$vgpr5' }
+  - { id: 2, class: vgpr_32 }
+body: |
+  bb.0:
+    %0 = IMPLICIT_DEF
+    %1 = IMPLICIT_DEF
+    KILL %1, %0
+    S_ENDPGM 0
+...