[PATCH] D100063: [AMDGPU] Split GCNRegBankReassign

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D100063#2674987 <https://reviews.llvm.org/D100063#2674987>, @rampitec wrote:

> In D100063#2674983 <https://reviews.llvm.org/D100063#2674983>, @arsenm wrote:
>
>> Can't this just skip virtual registers? Does it really need to know which mode its in?
>
> All registers are virtual here. It will skip a register if there is no assignment in VRM (and obviously skip physregs).
> This is slower as it is though. I can add the check "Reg.isPhysical() || !VRM->isAssignedReg(Reg)" earlier to mitigate it.
> Will that help?

Why is that slower?

I also would prefer with the allocation split that the final rewrite of registers was done at once at the end. It does commit the intermediate state now, although I don't remember why I did it that way


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