[PATCH] D100063: [AMDGPU] Split GCNRegBankReassign

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D100063#2675023 <https://reviews.llvm.org/D100063#2675023>, @arsenm wrote:

> In D100063#2674987 <https://reviews.llvm.org/D100063#2674987>, @rampitec wrote:
>
>> In D100063#2674983 <https://reviews.llvm.org/D100063#2674983>, @arsenm wrote:
>>
>>> Can't this just skip virtual registers? Does it really need to know which mode its in?
>>
>> All registers are virtual here. It will skip a register if there is no assignment in VRM (and obviously skip physregs).
>> This is slower as it is though. I can add the check "Reg.isPhysical() || !VRM->isAssignedReg(Reg)" earlier to mitigate it.
>> Will that help?
>
> Why is that slower?

Simply because I do that check late. It does not matter much until you split the RA. I can move the check earlier, that is not a big deal.

> I also would prefer with the allocation split that the final rewrite of registers was done at once at the end. It does commit the intermediate state now, although I don't remember why I did it that way

If you will run rewriter once no changes are needed at all. Just run the pass right before the rewriter. Although currently you are running it twice. What are your plans about this?


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