[PATCH] D99083: [RISCV] Introduce floating point control and state registers

Serge Pavlov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 7 20:47:05 PDT 2021


sepavloff added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1173
 
+def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
+def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
----------------
craig.topper wrote:
> Do we have use cases for all of these?
`ReadFRM` is used in the implementation of FLT_ROUNDS_ (D90854).
`WriteFRM` and `WrireFRMImm` are used in the implementation of set_rounding (D91242).
`SwapFRM` and `SwapFRMImm` are not used in any of pending patches but they are useful to implement target-specific optimization of the code pattern:
```
    int old_rm = fegetround();
    fesetround(new_rm);
    ...
    fesetround(old_rm);
```
which is likely to be used in the implementation of `#pragma STDC FENV_ROUND`.

Operations with FFLAGS are not used now. They would be needed to implement functions like `fetestexcept` and similar, but now there are no such attempts AFAIK.

Operations would be needed for target specific implementation of intrinsics that access FP control modes (D82525) and FP environment (D71742).


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:543
+// Special registers
+def FFLAGS : RISCVReg<1, "fflags">;
+def FRM    : RISCVReg<2, "frm">;
----------------
craig.topper wrote:
> Is there any significance the 1, 2, and 3 chosen for the first operand here?
The first operand of `RISCVReg` is `HWEncoding`, 1, 2 and 3 represent hardware addresses of the respective system registers which are specified in the RISCV specification (https://github.com/riscv/riscv-isa-manual/releases/download/draft-20210402-1271737/riscv-spec.pdf), chapter 25 (RV32/64G Instruction Set Listings), table 25.3 (RISC-V control and status register (CSR) address map).

On the other hand, these special registers are not used as operands in any of non-pseudo instruction, so these definitions are not used in instruction emitter. It means that particular values are not important, at least now.


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https://reviews.llvm.org/D99083



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