[PATCH] D99083: [RISCV] Introduce floating point control and state registers
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 7 11:34:29 PDT 2021
craig.topper added inline comments.
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1173
+def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
+def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
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Do we have use cases for all of these?
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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:543
+// Special registers
+def FFLAGS : RISCVReg<1, "fflags">;
+def FRM : RISCVReg<2, "frm">;
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Is there any significance the 1, 2, and 3 chosen for the first operand here?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D99083/new/
https://reviews.llvm.org/D99083
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