[PATCH] D99910: [RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2986
+    // Double the VL since we halved SEW.
+    SDValue VL = Op.getOperand(NumOps - 1);
+    SDValue I32VL =
----------------
frasercrmck wrote:
> I can't remember exactly how the intrinsics work but is it able to omit this if you're using `zero` as the vector length (i.e. VLMAX)?
Passing 0 to the intrinsic is really 0 not VLMAX. If you want VLMAX you would need to call one of the vsetvlmax_*() intrinsics before this and pass the return value which would be the real VLMAX for the vtype.

I suppose we could try to figure out that the producing instruction is a vsetvlmax intrinsic with SEW=64 vtype and create a new vsetvlmax intrinsic with SEW=32 to pass here.


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  https://reviews.llvm.org/D99910/new/

https://reviews.llvm.org/D99910