[PATCH] D99910: [RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32.
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 7 07:35:37 PDT 2021
frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.
Seems like a good strategy to me.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2986
+ // Double the VL since we halved SEW.
+ SDValue VL = Op.getOperand(NumOps - 1);
+ SDValue I32VL =
----------------
I can't remember exactly how the intrinsics work but is it able to omit this if you're using `zero` as the vector length (i.e. VLMAX)?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D99910/new/
https://reviews.llvm.org/D99910
More information about the llvm-commits
mailing list