[PATCH] D99910: [RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

Seems like a good strategy to me.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2986
+    // Double the VL since we halved SEW.
+    SDValue VL = Op.getOperand(NumOps - 1);
+    SDValue I32VL =
----------------
I can't remember exactly how the intrinsics work but is it able to omit this if you're using `zero` as the vector length (i.e. VLMAX)?


Repository:
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  https://reviews.llvm.org/D99910/new/

https://reviews.llvm.org/D99910