[PATCH] D98936: [RISCV] DAG nodes and pseudo instructions for CSR access

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff added a comment.

In D98936#2637803 <https://reviews.llvm.org/D98936#2637803>, @craig.topper wrote:

> So to provide alternate scheduling information, we need scheduler predicates to inspect the operands to find the system register?

Pseudos that operate on specific registers should get separate definitions, like:

  def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
  def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
  def SwapFRM : SwapSysReg<SysRegFRM, [FRM]>;

> And what pass would be responsible for adding implicit def/use of the rounding mode register?

I think the implicit use/def should be a property of FP instructions, but this is a topic for discussion (https://lists.llvm.org/pipermail/llvm-dev/2021-March/149177.html).


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