[PATCH] D98936: [RISCV] DAG nodes and pseudo instructions for CSR access

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:155
 
+def uimm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<12>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<12>;
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Does this need to inherit from Operand? Or need any of the Parser/Encoder/MCOperand etc? Could it just be an ImmLeaf down with simm32?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1178
+
+let hasSideEffects = 0, isCodeGenOnly = 1 in
+def Read_CSR : Pseudo<(outs GPR:$rd), (ins csr_sysreg:$reg),
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Doesn't read need side effects to say after earlier writes to it?


Repository:
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  https://reviews.llvm.org/D98936/new/

https://reviews.llvm.org/D98936