[PATCH] D99026: [RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64
Jessica Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 20 13:00:23 PDT 2021
jrtc27 added a comment.
In D99026#2639788 <https://reviews.llvm.org/D99026#2639788>, @craig.topper wrote:
> In D99026#2639787 <https://reviews.llvm.org/D99026#2639787>, @jrtc27 wrote:
>
>> I think the final line of your commit message is the wrong way round?
>
> Maybe it was poorly written. How does it look now?
Ah that makes more sense, I misunderstood what your point was
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D99026/new/
https://reviews.llvm.org/D99026
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